Low component count Wadley loop RX

After successfully acheiving very satisfying results with the Deltahet triple conversion RX using vacuum tubes, I thought to implement a similar design using silicon. I figured many functions can be integrated into modern "do it all" RF chips. The tuneable IF and detector functions can be wrapped up by using an AM radio chip, some even incorporate the Audio stages.

The actual loop itself could use an FM radio chip, these use a front end mixer with integral oscillator VHF capable, the usual 10.7 meg IF IF stages "should" function reasonably well at 37/38 megs, the oscillator easily handling the 40 to 70 meg oscillator frequency.

This leaves the signal front end. Again, another dedicated FM radio chip can utilised here, using the Rf amplifier and mixer section.

With just 3 ICs, it may just be possible. Of course, we need a SSB detector, this too can be done with a second AM radio chip, the oscillator becoming the BFO, the mixer being the product detector..... so thats just 4 ICs. Finally we need the 1 meg harmonic comb generator, one transistor will do this.

That leaves the tuned circuits, the L/C headache.

Reading JAGs post about filters and SMD coils, it seems possible to use off the shelf inductors and simple RF chokes for the required filters without complicated winding instructions.... seems noone likes coil winding and are actually frightened of them...... I have no experience with store bought colls and chokes, always being a wind my own type delinquent.

So, we need a 1 meg wide 40 meg bandpass filter, a 37.5 bandpass filter around 200kc wide , the tuneable IF coils tuning 2 to 3 megs, and anything to give us a 455kc 3rd IF for selectivity, this can be addressed with cheap ceramic filters, or possibly go down to a 100 kc last IF which will give very good selectivity with just L/C stages.... even a tad of regeneration.

The big issue is tuning the front end VFO, the front end BPF, and the tuneable IF.

Varicap diodes are no of use, the only alternative are tuning capacitors, the only tuning capacitors reasonably available are those horrid polyvaricons. Although better than Varicap diodes. these are temperature unstable and will require good robust reduction drives to work efficiently. This creates the biggest logistics problem with designing this radio.

The next issue is frequency readout, these days one microchip will do the deed. It will require the first two MSD of the 40 to 70 mhz VFO to be read, then subtract 40, the first IF, display that on the left two digits, then read the tuneable IF VFO, subtract the third IF and display that on the remaining right hand digits, this is much simpler than creating a mechanical display.

There will still be a requirement for some indication of preselect frequency on the front panel.

When thinking about this, I went off on a small tangent.

If we take the first 40 to 70 Mhz VFO and divide this by 10, that signal of 4 to 7 mHz can be inputted to a simple phase detector, the CMOS 74HCT4046 springs to mind, these are cheap, and can easily handle these low frequencies.. The other port sees a 100Kc xtal oscillator . As the 40mHz VFO is tuned, the phase detector will "lock" on each 1 meg boundary using the harmonics of the 100kc oscillator, This gives us 30 fixed oscillator signals 1 meg apart, offest by the first IF frequency of 40 megs. The PLL section sees a divided by 10 version of this.

Doing it this way, we get a lock indicator, we get a 4 to 7 meg signal easily processed in a very basic digital frequency readout, the 100kC master oscillator doubles as the BFO in the 100kC final IF. A frequency readout eliminates any tuning scales and mechanical effort.

Because we now have an oscillator frequency feedback loop, we can now use varicap diodes for the 40 to 70 mHz section without too many problems.

This negates the whole of the Wadley loop section, as no drift cancellation is required, now being handled by the rudimentary PLL, so simplifying the design further.

Polyvaricons are fine for the relatively course tuning of the front end preselector, this now only leaves the tuneable IF where the ultimate stability of the receiver depends.

Here we need a GOOD tuning capacitor and reduction drive for ease of tuning, already good, because each band is just 1 meg wide and the tuning rate is the same from 1 to 30 megs. With the final VFO tunes 2.1 to 3.1 megs, so drift should be tolerable using precision voltage regulators and quality multiturn pots.... as far as I am aware 3 gang polyvaricons are unavailable. The added advantage of varicaps here is three or even four gang TUNED second IF stages are easily possible, improving image rejection given the low 100kC third IF.

By further dividing the 100kC reference oscillator, say to 100HZ, its easily possible to use another PLL to serve as the main tuning, although adding another two chips......

Now, IF we are using varicaps, why not eliminate the switches on the front end BPFs and use diode switching here, there will be room in the MPU to easily do this, all it needs to do is compare the left hand frequency digits, we already have these, to a lookup table to activate the correct BPF as JAG explains in his design. If we have more spare room in the MPU, this could be extended to create a course tuning voltage for auto tuning of the front end preselector as well, eliminating the polyvaricon and using varicaps once again. Other than cross modulation issues, this is a reasonably non critical area for the varicap diode.

I think I count around 6 cheap and common ICs, a few transistors and diodes.....

So, thats where I am with this ......

to be continued