Designing class-A solid-state regen w/explicit AAC loop

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Designing class-A solid-state regen w/explicit AAC loop Post by qrp-gaijin » Wed Oct 30, 2013 Transistors, IC's and other new fangled devices forum qrp-gaijin Posts: 2822 Joined: Sun Feb 28, 2010 2:12 pmContact:Designing class-A solid-state regen w/explicit AAC loop vladn wrote: qrp-gaijin wrote:I assume there is nothing fundamental to the idea that would preclude a solid state implementation, correct? I just like playing with tubes. You can replace 6AS6 with a 3-transistor half-Gilbert cell and get more gain and long term stability. Is it possible to use JFETs or must BJTs be used? The fact that both ends of the hybrid feedback network are connected to grids, combined with the fact that grid current is flowing, leads me to believe that JFETs cannot be used in this configuration because then no current would flow through gates and thus no current would flow through the hybrid feedback network. (Edit: I guess one of the grids is acting more like a JFET drain? See attempted JFET circuit below.) vladn wrote:Needs a bit different biasing though. That seems to be an understatement. Even after reviewing all the threads and related links I cannot figure out what is going on with R5 (seems intended to pull the grid bias down?), or how to translate that, and the complex plate network with all the diodes, into a BJT half-Gilbert-cell arrangement. I have something sketched out with three BJTs but it looks utterly implausible. If you might have time to sketch up a suggested framework for a solid state implementation, it would be most helpful. --- EDIT: OK, instead of starting from your most-complicated "3 controls" circuit I decided to try again starting with your least-complicated synchrodyne circuit: vladn wrote:The simplest possible solution to the inter-dependent regeneration controls is to use the receiver as a pure synchrodyne [...] Here is a possible circuit diagram for such synchrodyne. This is the simplest variant of the 6AS6 AAC detector I can think of: Starting from this circuit, I managed to come up with the following plausible-looking JFET circuit. Does the circuit arrangement look reasonable? I think it makes sense along the lines of the explanation you gave for the circuit operation. I'm not sure however if the gate on JFET U3 is doing it's job correctly to regulate the oscillator amplitude, though it seems like it might: as the oscillation amplitude across RFC2 increases, the positive peaks only get through D2, are filtered by C9/RFC3/C10, and pull the gate voltage up, restricting the U3 source-drain channel; but I'm not sure if this alone is enough to affect the feedback loop going through U1, U2, and the hybrid feedback network. What do you think? 6as6-jfet.png (77.04 KiB) Viewed 4182 times qrp-gaijin Posts: 2822 Joined: Sun Feb 28, 2010 2:12 pmContact:Re: Designing class-A solid-state regen w/explicit AAC loop Postby qrp-gaijin » Wed Oct 30, 2013 2:21 am Continuing this thread from the tube forum (original post here: viewtopic.php?p=45792#p45792 vladn wrote:The RF path is almost OK, but the biasing is not quite right. You need to shift up the U310_2 gate above ground. It can be a place to add the conventional regen control but there are some subtle things that suggest a slightly different solution. As I mentioned before, some time ago I started working on a triple-fet detector along these lines. It did not pass my internal "QC" after one evening of testing and I shelved it. There was nothing fundamentally wrong with it, it just required a bit more work on the loop stability. Could you expand on what the "slightly different solution" could look like? My circuit translation is mostly mechanical, and as I said, I'm not really sure if the AAC loop through U310_3 will work as drawn, or even how it is really supposed to work. Multiple grids, half-Gilbert cells, separate limiters, control loops - it's all somewhat foreign to me! vladn Posts: 853 Joined: Sun Nov 02, 2008 7:15 amLocation: NJ, USARe: Designing class-A solid-state regen w/explicit AAC loop Postby vladn » Wed Oct 30, 2013 2:53 am Here are some notes for the circuit: 1. U310_2 and U310_3 gates should both be biased positively in normal operation, otherwise U310_1 will be starved of Vds. The simplest way to do it is to apply regen control voltage from the potentiometer to the gate of U310_2. But there is a better way (see #3) 2. Such configuration made with JFETs is not a true Gilbert cell. The real thing is a translinear circuit and requires exponential characteristics of a bipolar transistors in the upper pair. But I think this is not an issue at all in this particular case. It just means that O=X*Y operation will be linear in X but not exactly linear in Y, where X is the RF signal (U310_1 gate) and Y is the control loop voltage (applied to U310_3 gate in your case). The circuit operates very close to a constant Gm value and Y will change very little (this is specific to linear feedback amp). 3. Subtle thing (as promised). The aperiodic load of the U310_3 has generally a higher impedance and higher voltage than the feedback path load of the U310_2. For better performance the gate must be grounded for RF with a relatively large value capacitor C8, say few nF or more. This will induce extra phase delay in the control loop, which is undesirable. It is better to apply the loop control voltage to the feedback branch (but with the opposite polarity of course), there the gate grounding cap can have a smaller value (few hunded pF, like the 6AS6 equivalent). 4. JFETs have quite a bit of cutoff voltage variation, so expect some need for a regen range trim. 5. If you plan to use it close to / below the threshold you may want to add the detector bias at some future point (or perhaps use germanium diodes). For now keep it simple though. When I get time I will sketch my variant of this, but I think you are on a right path. qrp-gaijin Posts: 2822 Joined: Sun Feb 28, 2010 2:12 pmContact:Re: Designing class-A solid-state regen w/explicit AAC loop Postby qrp-gaijin » Wed Oct 30, 2013 10:12 am vladn wrote:1. U310_2 and U310_3 gates should both be biased positively in normal operation, otherwise U310_1 will be starved of Vds. The simplest way to do it is to apply regen control voltage from the potentiometer to the gate of U310_2. But there is a better way (see #3) [...] 3. [...] It is better to apply the loop control voltage to the feedback branch (but with the opposite polarity of course), there the gate grounding cap can have a smaller value (few hunded pF, like the 6AS6 equivalent). Something like this? 6as6-jfet-2.png (30.49 KiB) Viewed 4131 times My circuit analysis is: 1. Without U310_3 present, U310_1 and U310_2 simply form something like a dual-gate-MOSFET or a cascode regenerative receiver, with the bias on the upper gate controlling regeneration with the R7 wiper. 2. With U310_3 present, it takes the amplified (buffered) signal from the tank through U310_1, amplifies it even further, and sends only the negative peaks through D2, which are smoothed by C9/RFC3/C10 to form a negative control voltage applied to the bottom of R7. As the tank signal amplitude increases, the negative control voltage increases, pulling the R7 wiper closer to ground and biasing U310_2 closer to pinch off, thus reducing the gain of the cascode pair U310_1 and U310_2 to control the oscillation amplitude. U310_3 thus forms an explicit automatic amplitude control (AAC) loop that is outside of the RF feedback path (U310_1 and U310_2), so (somehow?) U310_1 and U310_2 can be biased to remain always in class A operation. I'm not exactly sure how to compute the bias though; R6 and R7 will need to be adjusted, but R7 also affects the effect of the AAC loop control voltage that the U310_2 gate sees. Another area I'm not sure about concerns the nuances of R1 and R3 operation. In particular, R3 is supposed to be scale-invariant, a concept which I am still wrapping my head around, and R1 is some sort of a filter. Will the above circuit arrangement allow proper operation of these controls? DrM Posts: 1027 Joined: Fri Jun 19, 2009 8:30 pmLocation: The NetherlandsRe: Designing class-A solid-state regen w/explicit AAC loop Postby DrM » Wed Oct 30, 2013 11:19 am You should better build an oscillator consisting of a differential pair made of two FET's or BJT's. The tail FET or BJT acts as a current source which controls the regeneration. More info, see topic "Adding ALC to a VCO?" at http://www.theradioboard.com/rb/viewtop ... =automatic and topic "A Shortwave receiver with automatic regeneration control" at http://www.theradioboard.com/rb/viewtop ... =automatic. But keeping a regen with an ALC-loop on the verge of oscillating is very difficult. It requires a PID-control loop. Schematic: vladn Posts: 853 Joined: Sun Nov 02, 2008 7:15 amLocation: NJ, USARe: Designing class-A solid-state regen w/explicit AAC loop Postby vladn » Wed Oct 30, 2013 1:05 pm DrM wrote:It requires a PID-control loop. Correct, this is what the 6as6 detector does. Keeping the regenerative amplifier in the linear class A mode requires additional amplification either at DC after the detector or at RF before the detector. The later has the advantage of operating the detector itself above the quadratic region and absence of DC drift issues (especially important with tubes). Below is one possible way to connect 3 JFETs together to make a rough equivalent of a 6AS6 circuit. Tried to keep potentiometer names the same between the JFET and 6AS6 schematics. I am lifting the diode detector ground (A) to control the regeneration the "old way". The target amplitude appears at A, the detected amplitude is subtracted from the target and the difference (loop error signal) appears at point "B", together with the AF signal. The loop error signal passes the low pass filter R1,C9 which essentially controls the ratio of proportional and integral error terms and biases the differential pair. The circuit is just a sketch, I have not tested it as drawn, it will likely need tweaks and optimizations. jfet_equiv_1.GIF (12.25 KiB) Viewed 4093 times One word of warning, the 6AS6 circuit has 10x lower gain for the DC control voltage "C". I had some loop stability issues at large amplitudes with a similar JFET equivalent (6as6 variant has no stability problems). I did not have time to work on it and analyze the loop phase margin. qrp-gaijin Posts: 2822 Joined: Sun Feb 28, 2010 2:12 pmContact:Re: Designing class-A solid-state regen w/explicit AAC loop Postby qrp-gaijin » Wed Oct 30, 2013 3:34 pm vladn wrote:Below is one possible way to connect 3 JFETs together to make a rough equivalent of a 6AS6 circuit. Thanks - it should provide a good baseline for further investigation. Before building any circuit, I plan to simulate it. What behavior should I look for to ensure the amplifier is always operating in class A? Could I simply, for example, monitor the current through R6, and if the current never cuts off, then it's class A and everything is fine? At some point I also want to incorporate wideband varactor tuning instead of the variable capacitor (it seems feasible even with hybrid feedback as I mentioned in another thread). Since the oscillation amplitude is explicitly controllable in this circuit, I expect there should be no problems with RF rectification at the tuning diode as long as the amplitude is kept within bounds (with trims on the appropriate pots). Any objections? One interesting limitation however might be that due to the need for low tank voltages, the maximum oscillation amplitude (before varactor distortion kicks in) will be less with a varactor than with a variable capacitor; such a varactor-imposed limitation on oscillation amplitude might reduce the benefit of the oscillation amplitude control, because it might no longer be possible to increase the oscillation amplitude to the desired high level for direct-conversion-like performance. One solution would then be the back-to-back varactor idea which should allow a larger oscillation amplitude (perhaps much larger?) without detuning. vladn Posts: 853 Joined: Sun Nov 02, 2008 7:15 amLocation: NJ, USARe: Designing class-A solid-state regen w/explicit AAC loop Postby vladn » Wed Oct 30, 2013 6:04 pm I have redrawn the detector section in a bit more readable form (I hope) and added a detector bias resistor R10 (it's value depends on the diodes used). jfet_equiv_2.GIF (12.28 KiB) Viewed 4054 times You can add a 50uA panel meter in series with the R4 like I did in my 6AS6 test setup. It helps monitor the amplitude while experimenting with R7,R3 dual amplitude controls, otherwise you can easily exit the linear range. In practice I rarely use R3, but it make a good theory demo As I said before I have very little experience with varactors. They have losses that depend on both frequency and amplitude and I have no good quantitative feeling on these. The Q(a,f) may have significant implications on the tilt control and linearity assumptions. I'd stick with the plain air variable capacitor for the initial experiments and only once you get the reference design working try adding varactors. The tank amplitude (before the C3,C4 divider) is fairly high. Last edited by vladn on Wed Oct 30, 2013 6:13 pm, edited 2 times in total. DrM Posts: 1027 Joined: Fri Jun 19, 2009 8:30 pmLocation: The NetherlandsRe: Designing class-A solid-state regen w/explicit AAC loop Postby DrM » Wed Oct 30, 2013 6:09 pm @Vladn: Below is one possible way to connect 3 JFETs together to make a rough equivalent of a 6AS6 circuit. Tried to keep potentiometer names the same between the JFET and 6AS6 schematics. I am lifting the diode detector ground (A) to control the regeneration the "old way". The target amplitude appears at A, the detected amplitude is subtracted from the target and the difference (loop error signal) appears at point "B", together with the AF signal. The loop error signal passes the low pass filter R1,C9 which essentially controls the ratio of proportional and integral error terms and biases the differential pair. The circuit is just a sketch, I have not tested it as drawn, it will likely need tweaks and optimizations. But where is the derivative term which looks at the speed of change of the error signal with time, dU/dT? vladn Posts: 853 Joined: Sun Nov 02, 2008 7:15 amLocation: NJ, USARe: Designing class-A solid-state regen w/explicit AAC loop Postby vladn » Wed Oct 30, 2013 6:16 pm DrM wrote:But where is the derivative term which looks at the speed of change of the error signal with time, dU/dT? There is none, it is a PI-regulator as drawn and tested in the 6AS6 circuit. I guess adding a derivative term can be useful for loop stability tweaks, but the 6AS6 detector is perfectly stable over a very wide range of control settings, more than enough for any practical purpose. DrM Posts: 1027 Joined: Fri Jun 19, 2009 8:30 pmLocation: The NetherlandsRe: Designing class-A solid-state regen w/explicit AAC loop Postby DrM » Wed Oct 30, 2013 6:21 pm vladn wrote:There is none, it is a PI-regulator as drawn and tested in the 6AS6 circuit. I guess adding a derivative term can be useful for loop stability tweaks, but the 6AS6 detector is perfectly stable over a very wide range of control settings, more than enough for any practical purpose. Is the ALC-loop in a superhet or in a simple cassette recorder with ALC also a PI-regulator? vladn Posts: 853 Joined: Sun Nov 02, 2008 7:15 amLocation: NJ, USARe: Designing class-A solid-state regen w/explicit AAC loop Postby vladn » Wed Oct 30, 2013 6:39 pm DrM wrote:Is the ALC-loop in a superhet or in a simple cassette recorder with ALC also a PI-regulator? The simple ones are I-only (approximately using an integrating RC network). The reality is more complex - this detector is a second order loop (first integrator is the tank itself) with exponential non-linearity. It can be modeled but the analytical solution is tricky. qrp-gaijin Posts: 2822 Joined: Sun Feb 28, 2010 2:12 pmContact:Re: Designing class-A solid-state regen w/explicit AAC loop Postby qrp-gaijin » Thu Oct 31, 2013 1:08 am vladn wrote:You can add a 50uA panel meter in series with the R4 like I did in my 6AS6 test setup. It helps monitor the amplitude while experimenting with R7,R3 dual amplitude controls, otherwise you can easily exit the linear range. In practice, how can you confirm if you are in the linear range or not? vladn wrote:The tank amplitude (before the C3,C4 divider) is fairly high. How do you compute or measure this? I suppose one way would be to measure the J2 gate voltage, then use the C3/C4 ratio to determine the voltage step-up, which then must be the tank voltage. Or is there some other way? And, isn't it possible to achieve an arbitrarily small oscillation amplitude (and hence an arbitrarily small tank voltage) using the amplitude control? Or is there some lower bound on the minimum achievable oscillation amplitude? (This is another fundamental area that is murky for me, how final oscillation amplitude is actually achieved in practice due to the loop stabilization.) vladn Posts: 853 Joined: Sun Nov 02, 2008 7:15 amLocation: NJ, USARe: Designing class-A solid-state regen w/explicit AAC loop Postby vladn » Thu Oct 31, 2013 1:57 am qrp-gaijin wrote:In practice, how can you confirm if you are in the linear range or not? In 6AS6 detector the transition is quite obvious, the frequency is constant up to a point and then starts shifting rapidly. I think 1-2V at the output of the detector should be safe. qrp-gaijin wrote:How do you compute or measure this? I suppose one way would be to measure the J2 gate voltage, then use the C3/C4 ratio to determine the voltage step-up, which then must be the tank voltage. Or is there some other way? If you have a scope this is the easiest way. Otherwise you can guess from the output amplitude, but you have to shunt the RFC1 with say 5k and use the U310 Gm value from the datasheet for a measured steady state current to estimate the gate AC voltage. qrp-gaijin wrote:And, isn't it possible to achieve an arbitrarily small oscillation amplitude (and hence an arbitrarily small tank voltage) using the amplitude control? Or is there some lower bound on the minimum achievable oscillation amplitude? With a biased detector the transition into oscillation is very smooth (based on the 6AS6 detector observations). You can get quite small amplitude, the loop will have another quadratic non-linearity but it does not seem to cause any troubles. The only issue is the loop stability range, the DC gain is about 10x higher in this JFET circuit vs the 6AS6 detector. Not sure what would be the acceptable range of adjustments for R1,R3,R7. qrp-gaijin Posts: 2822 Joined: Sun Feb 28, 2010 2:12 pmContact:Re: Designing class-A solid-state regen w/explicit AAC loop Postby qrp-gaijin » Thu Oct 31, 2013 10:17 am vladn wrote:As I said before I have very little experience with varactors. They have losses that depend on both frequency and amplitude and I have no good quantitative feeling on these. The Q(a,f) may have significant implications on the tilt control and linearity assumptions. vladn wrote: qrp-gaijin wrote:In practice, how can you confirm if you are in the linear range or not? In 6AS6 detector the transition is quite obvious, the frequency is constant up to a point and then starts shifting rapidly. It should be possible to compare the varactor nonlinearity with the variable capacitor nonlinearity. One could perhaps build the circuit with a variable capacitor, then observe the oscillation amplitude (or the microammeter current) at which non-linear losses appear, which is when the frequency starts shifting rapidly. Plot a graph of this nonlinearity threshold vs. frequency. Then, replace the variable capacitor with a varactor, and make the same graph. The nonlinearity onset should happen at a lower oscillation amplitude if the varactor has more nonlinear losses than the capacitor. It might be the case that the varactor nonlinear losses are small compared to the other circuit nonlinear losses, in which case the onset of nonlinearity for the varactor case and the variable capacitor case would be the same. The circuit would need to be tweaked beforehand to ensure that it will oscillation is possible in both the case with varactor tuning and the case with variable capacitor tuning (since the varactor has greater losses more feedback will likely be needed). Then to test the Q(a,f) difference between the variable capacitor and varactor all circuit constants should be kept the same and only the tuning mechanism changed. Sounds like a lengthy investigation. Maybe I'll get around to it someday... The reason, of course, that I'm so interested in varactor tuning is that combining a varactor with a ten-turn pot makes a compact and fairly easy-to-obtain wideband tuning mechanism. You mentioned in the 6as6 tube thread the difficulty of procuring high-quality slow-rate tuning capacitors for your circuit. Perhaps you might also consider investigating varactor tuning.